VHDL编程问题 总是提示 Error (10593): VHDL Variable Assignment Statement error at paomadeng.vhd(25):

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY paomadeng IS
PORT(clk:IN std_logic;
light:OUT std_logic_vector(0 TO 7));
END paomadeng;

ARCHITECTURE one OF paomadeng IS
SIGNAL temp: std_logic_vector(0 TO 7):="10000000";
SIGNAL flag:std_logic_vector(0 to 2):="000";

BEGIN
P1:PROCESS(clk,temp)

BEGIN
IF(clk'event and clk='1')THEN
IF(flag="000")THEN
FOR j IN 0 TO 7 LOOP
temp(j)<='0';
IF(j/=7)THEN
temp(j+1)<='0';
j:=j+1;
ELSIF(temp(7)='1')THEN
flag<="001";
EXIT;
END IF;
light<=temp;

END LOOP;
END IF;
IF(flag="001")THEN
FOR j IN 7 DOWNTO 0 LOOP
temp(j)<='0';
IF(j/=0)THEN
temp(j-1)<='1';
j:=j-1;
ELSIF(temp(0)='1')THEN
flag<="000";
EXIT;

END IF;
light<=temp;

END LOOP;
END IF;
END IF;
END PROCESS P1;

END one;

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Error (10593): VHDL Variable Assignment Statement error at paomadeng.vhd(25): target object "j" must be variable or aggregate
用你的程序运行了下是这个错误提察纤示，表示的是j这个赋值方式有败皮仿问题。
：=是变量的赋值方式，握伏<=是信号的赋值方式

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